One class of nonvolatile memory devices includes electrically erasable programmable read only memory (EEPROM), which may be used in many applications including embedded applications and mass storage applications. In typical embedded applications, an EEPROM device may be used to provide code storage in personal computers or mobile phones, for example, where fast random access read times may be required. Typical mass storage applications include memory card applications requiring high capacity and low cost.
One category of EEPROM devices includes NAND-type flash memories, which can provide a low cost and high capacity alternative to other forms of nonvolatile memory. A typical NAND-type flash memory includes a plurality of NAND-type strings therein that are disposed side-by-side in a semiconductor substrate. Each EEPROM cell within a NAND-type string includes a floating gate electrode and a control gate electrode, which is electrically connected to a respective word line. These EEPROM cells may be cells that support a single or a multi-level programmed state. EEPROM cells that support only a single programmed state are typically referred to as single level cells (SLC). In particular, an SLC may support an erased state, which may be treated as a logic 1 storage value, and a programmed state, which may be treated as a logic 0 storage value. The SLC may have a negative threshold voltage (Vth) when erased (e.g., −3V<Vth<−1V) and a positive threshold voltage when programmed (e.g., 1V<Vth<3V).
The state of an EEPROM cell may be detected by performing a read operation on a selected cell. As will be understood by those skilled in the art, a NAND string will operate to discharge a precharged bit line BL when a selected cell is in an erased state and a selected word line voltage (e.g., 0 Volts) is greater than the threshold voltage of the selected cell. However, when a selected cell is in a programmed state, the corresponding NAND string will provide an open circuit to the precharged bit line because the selected word line voltage (e.g., 0 Volts) is less than the threshold voltage of the selected cell and the selected cell remains “off”. Other aspects of NAND-type flash memories are disclosed in U.S. application Ser. No. 11/358,648, filed Feb. 21, 2006, and in an article by Jung et al., entitled “A 3.3 Volt Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1748-1757, November (1997), the disclosures of which are hereby incorporated herein by reference.
Operations to program or erase an EEPROM cell may include the application of a relatively high program or erase voltage to the control electrode or channel region of the EEPROM cell, respectively. As will be understood by those skilled in the art, the magnitude of a program voltage should be sufficient to attract a sufficient number of electrons to a floating gate electrode within the cell and the magnitude of the erase voltage should be sufficient to withdraw a high percentage of accumulated electrons from the floating gate electrode. These operations to attract electrons to the floating gate electrode or withdraw electrons from the floating gate electrode result in a change in a threshold voltage of the EEPROM cell. In particular, operations to program an EEPROM cell may result in an increase in the threshold voltage of the EEPROM cell and operations to erase an EEPROM cell may result in a decrease in the threshold voltage of the EEPROM cell, as described above for both single and multi-level cells.
Unfortunately, as EEPROM devices become more highly integrated on a semiconductor substrate, the parasitic capacitance between floating gate electrodes of closely adjacent EEPROM cells may increase. As illustrated by FIGS. 1A-1C, this parasitic capacitance is directly proportional to the area of overlap between adjacent floating gate electrodes and inversely proportional to the lateral distance between adjacent floating gate electrodes. This lateral distance is typically reduced as the level of device integration increases. In particular, FIG. 1A illustrates an array of NAND-type EEPROM devices, which includes a plurality of floating gate electrodes 19 spaced side-by-side in two dimensions (e.g., row and column directions). These floating gate electrodes 19 are separated from active regions 13 of a semiconductor substrate 11 by tunnel insulating layers 17. These active regions 13 are defined by spaced-apart trench isolation regions 15. The control electrodes of each EEPROM cell within a row are commonly connected to respective word lines 23 (shown as word lines A, B and C). Each floating gate electrode 19 is separated from a corresponding word line by an inter-gate dielectric layer 21. As illustrated by FIGS. 1B-1C, the floating gate electrodes 19 are spaced apart from each other in a bit line direction by source/drain regions 25 and are spaced apart from each other in a word line direction by the trench isolation regions 15. The area of overlap between each floating gate electrode in the bit line direction is equivalent to the product h1W1 and the area of overlap between each floating gate electrode in the word line direction is equivalent to the product h1×W2.
These increases in parasitic capacitance caused by higher device integrated levels can result in a corresponding increase in floating gate interference. If this interference is sufficiently high, then the programming of one EEPROM cell may result in a threshold voltage shift of one or more closely adjacent EEPROM cells in the neighborhood of the EEPROM cell undergoing programming. Such shifts in threshold voltage can reduce memory device reliability by causing bit errors to occur during data reading operations. These and other consequences of increased parasitic capacitance between floating gate electrodes are described in an article by Jae-Duk Lee et al. entitled “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, Vol. 23, No. 5, pp. 264-266, May (2002).